1. Field of the Invention:
The present invention relates to a phase synchronizing circuit for quickly and accurately synchronizing the phases of a receiver and transmitter in information transmission systems such as facimile systems.
2. Discussion of the Prior Art:
Generally, in information transmission systems such as facsimile systems or the like, it is difficult to reproduce at the receiver a clear-cut and distinct image whenever the receiver signal phase is not synchronized with that of the transmitter. For this reason, a follow-up type synchronizing circuit has been conventionally employed for synchronizing the receiver phase and that of the transmitter. A follow-up synchronizing circuit reduces for an optional period the speed of a driving motor at the receiver to thereby effectuate synchronization of the receiver phase with that of the transmitter during the course of that period.
In FIG. 1 are shown waveforms which illustrate the operation of the above prior art synchronizers. A phase signal B.sub.1 (see FIG. 1(B)) is generated at the receiver each time a reception drum (not shown) makes one revolution and a phase signal A.sub.1 (see FIG. 1(A)) is generated at the transmitter each time a transmission drum makes one revolution. A.sub.1 and B.sub.1 are applied to a follow-up type phase synchronizing circuit provided at the receiver side and the time T.sub.1 between the leading edges of pulse signals A.sub.1 and B.sub.1 is detected. The larger the phase deviation between the receiver and transmitter, the longer time T.sub.1 is, and, in response thereto, the follow-up type phase synchronizing circuit reduces the reception drum driving frequency to a frequency less than the rated frequency thereof for the length of time T.sub.1. Thus, the number of revolutions per unit time of the reception drum is reduced to a rate less than that of the transmission drum for a length of time T.sub.1. For example, when a phase deviation T.sub.1 is detected, the driving frequency of the reception drum driving motor, initially driven at 84Hz, is changed to 63Hz for the length of time T.sub.1. After time T.sub.1 passes, the motor is again driven at 84Hz. Subsequently, when phase signals A.sub.2 and B.sub.2 are generated at the transmitter and receiver, respectively, time T.sub.2 (T.sub.2 .ltoreq. T.sub.1) between the leading edges of signals A.sub.2 and B.sub.2 is detected, and the reception drum is decelerated for the time T.sub.2 in the manner described above.
The above is repeated several times until synchronization is completed between the transmitter phase and that of the receiver.
However, the foregoing conventional synchronizing circuitry has an inherent defect in that there is a limit to the precision of phase matching. That is, if time T.sub.2 between the leading edges of signals A.sub.2 and B.sub.2 is around 10m sec or less, the speed of the reception drum driving motor may remain unchanged, even though the input frequency of the motor is changed from 84Hz as shown in FIG. 1 (C) to 63Hz shown in FIG. 1 (D).